This invention relates generally to circuits for the comparison of the phase or the frequency of two input signals, and, more particularly, to digital circuits for the detection of phase or frequency differences between two digital, or digitized, input signals.
Circuits for the quantitative detection of a difference between the frequencies of two signals, or of a phase difference between two signals of equal or nearly equal frequency, are useful in a variety of applications, particularly in communication systems. In a conventional circuit implementation of a digital phase and frequency detector, each of the input signals takes the form of a train of rectangular pulses, which is first differentiated to define a rising or falling edge of each pulse. The resulting signal is then applied as an input to a memory device, such as a flip-flop, of which there is one for each input signal. Differentiation may be performed inherently in the flip-flops, which typically operate in response to a rising or falling edge of a clock pulse, and which, for purposes of explanation, are referred to as the first and second flip-flops.
The logical states of the two flip-flops are determined both by the respective inputs derived from the two digital input signals, and by the operation of a feedback circuit, which controls the states of the flip-flops in response to detection of particulaar current combined states. More specifically, each of the flip-flops can be so connected as to be set to a logical "one" upon the detection of a falling edge of an input signal applied to its clock terminal. The feedback circuit is typically implemented in the form of an OR gate, the inputs of which are derived from the inverted outputs of the flip-flops, and the output of which is applied to clear both flip-flops to a logical zero when the OR gate output is a logical zero. Consequently, when an attempt is made to set both of the flip-flops, the OR gate inputs are zeros and a zero OR gate output immediately clears both of the flip-flops. The "both set" condition of the flip-flops is termed a forbidden state or condition in such a circuit. As will shortly become apparent, the performance of the circuit will be significantly improved by minimization of the time spent in the forbidden state.
If the first flip-flop receives input signals at a higher frequency than the second flip-flop, the first flip-flop will be set upon the detection of the falling edge of a pulse of the first input signal, and will be reset upon subsequent detection of the falling edge of a pulse of the second input signal. The second flip-flop, on the other hand, will remain cleared or reset, since the next-occurring input pulse after the flip-flops have been cleared will be supplied by the higher frequency input signal, which will set the first flip-flop again. Thus, the second flip-flop will stay reset so long as the frequency of the signal applied to it is less than the frequency of the signal applied to the first flip-flop. The characteristic output condition for the two flip-flops in such a circuit is that there is one so-called "enabled" flip-flop, which produces a digital output signal, the duty cycle of which varies in accordance with the input signal frequency difference, and a so-called "disabled" flip-flop with a logical zero output. The identity of the enabled and disabled flip-flops changes only when the frequency difference changes sign, i.e. when the input signal of lower frequency becomes the one of higher frequency.
In one common arrangement for producing an analog signal representative of the input signal frequency difference, the digital output from each of the flip-flops is low-pass filtered, and then applied to a subtractor circuit, by means of which one signal is subtracted from the other to produce a signed analog output. Thus, for example, the first flip-flop can be arranged to produce a positive analog output when it is enabled, and the second flip-flop to produce a negative analog output when it is enabled.
Difficulties with this conventional design arise principally from the fact that circuit reaction times are not zero, as assumed in the foregoing discussion. In order for both flip-flops to be reset to a logical zero state, their outputs must both be set to logical ones for a short period of time. If the frequency of the input signals is low enough, the duration of this forbidden state will be quite small relative to the period of the input signals, and may not significantly affect the operation of the circuit. The effect of these brief occurrences of the forbidden state will be to produce narrow output pulses from the disabled flip-flop. Although these narrow pulses might be suppressed by appropriate filtering, it will be apparent that the filtered output voltage from the disabled side of the circuit will then be approximately constant for a constant frequency of the input signal to that side, since a forbidden-state pulse will be produced for each pulse applied to the disabled flip-flop. Moreover the effect of the narrow, forbidden-state pulses will become more significant as the output of the enabled side approaches zero.
Another form of degradation in the performance of a phase-frequency detector of this type occurs when triggering pulses to each side of the circuit are so close together in time that complete setting and resetting operations cannot be performed. This indeterminate toggling of the outputs may result in a zero output signal for some distance on each side of the in-phase condition, yielding a "dead zone" in the output characteristic of the circuit, which is the variation of the output signal plotted against the phase difference between the input signals.
The size of the dead zone is further increased due to the fact that resetting operations for the conventional digital phase-frequency detector circuit are performed in a series timing relationship with the setting operations. There are additional time delays associated with the feedback circuit, and these also affect the resetting operation. These feedback delays include an OR gate delay, as well as any additional memory delay that may be needed to ensure the clearing of both flip-flops in response to a common control signal derived from both flip-flop outputs. The dead zone in the phase characteristic of a circuit of this type represents a total time delay that is approximately constant for a given circuit, and provides a convenient means for comparing the performances of various phase-frequency detector circuits.
It will be apparent from the foregoing that there is a significant need for a digital phase-frequency detector circuit in which both the inherent circuit time delays and the occurrence of forbidden states of the flip-flops are both minimized, to provide a reduced dead zone at any given frequency, or to provide higher frequency capability for a given dead zone. The present invention fulfills this need.